1. Field of Invention
The present invention relates generally to mass digital data storage systems. More particularly, the present invention relates to systems and methods for tightening the erased bit threshold voltage distribution associated with a sector to effectively improve the performance of read operations associated with the sector.
2. Description of the Related Art
The use of non-volatile memory systems such as flash memory storage systems is increasing due to the compact physical size of such memory systems, and the ability for non-volatile memory to be repetitively reprogrammed. The compact physical size of flash memory storage systems facilitates the use of such storage systems in devices which are becoming increasingly prevalent. Devices which use flash memory storage systems include, but are not limited to, digital cameras, digital camcorders, digital music players, handheld personal computers, and global positioning devices. The ability to repetitively reprogram non-volatile memory included in flash memory storage systems enables flash memory storage systems to be used and reused.
Flash memory storage systems generally include flash memory cells. A flash memory cell may include a transistor with a source and a drain that are formed in a silicon substrate, or a flash memory cell may include a source and a drain that are formed in a well within a silicon substrate. Hence, sectors associated with a flash memory card generally include multiple transistors. When a flash memory cell is programmed, a relatively large voltage may be applied to a drain while a source is grounded, and a larger voltage may be applied to a control gate to raise the voltage potential of a floating gate, as will be understood by those skilled in the art. Programming a memory cell generally involves substantially injecting electrons into a floating gate to create a desired threshold voltage for the memory cell. A desired threshold voltage may be considered to be a voltage that is applied to the control gate of the memory cell to allow conduction to occur through a channel region during a read operation.
A cell that is programmed may be erased. When multiple cells or bits within a sector are erased, a distribution of the bits may be created. FIG. 1 a is a diagrammatic representation of a plot of an erased bit threshold voltage distribution associated with a sector of a memory card. A plot 110 includes an axis 112 which represents a number of bits and an axis 114 which represents the threshold voltage (VT) associated with a sector or, more specifically, of transistors associated with the sector. An erased bit threshold voltage distribution 116 indicates the disposition of cells or bits associated with a sector or a block. It should be appreciated that the shape of distribution 116 may vary widely and, for purposes of illustration, has been exaggerated. Bits that are most erased or over-erased are reflected in a trailing edge 118, while bits that are least erased are reflected in a leading edge 120.
An erase verify level (ERV1) 122 is generally defined such that preferably all bits in distribution 116 fall below ERV1122. Typically, ERV1122 may be set at a negative voltage level, e.g., approximately xe2x88x920.8 Volts (V), that enables a margin 124 between ERV1122 and a read level 126 to be maintained. When any bit exceeds read level 126, that bit will generally be read.
When most erased bits, or bits at trailing edge 118 of distribution 116, are too negative, the performance of the overall memory device which includes the sector associated with the bits may be compromised. As will be appreciated by those skilled in the art, most erased or over-erased bits are often associated with transistors which have a relatively low voltage level, e.g., a voltage level of approximately xe2x88x923.0 V or less. When the voltage level of a transistor is too low, current may be conducted through the transistor. By way of example, leakage currents may flow through the transistor as a result of floating gates associated with the transistors substantially losing electrons. When current is conducted through the transistor due to a voltage that is very negative, the sensing and programming associated with the sector may occur less efficiently. Over-erased or most erased bits also generally take longer to erase than other bits and, as a result, substantially define the erase time associated with substantially all bits of the sector
To correct for the most erased bits, distribution 116 may effectively be shifted through the use of a process such as soft programming. Soft programming, as will be appreciated by those skilled in the art, generally involves applying a voltage which effectively shifts most erased bits to a higher voltage level. During soft programming, a relatively high voltage may be provided to a transistor which effectively causes electrons to be pulled onto the floating gate associated with the transistor. In other words, electrons may effectively be injected into the floating gate.
When most erased bits are corrected using soft programming, least erased bits, or bits associated with leading edge 120 of distribution 116 are affected. Specifically, distribution 116 is shifted such that most erased bits and least erased bits are substantially all less negative. As shown in FIG. 1b, distribution 116 may shift such that after a soft program, distribution 116 becomes shifted distribution 116xe2x80x2. For purposes of illustration, the amount by which distribution 116 shifts to become shifted distribution 116xe2x80x2 has been exaggerated. Typically, a soft program will be stopped when a certain number of bits have exceeded ERV1122. That is, when the number of xe2x80x9cfailing bitsxe2x80x9d exceeds a threshold, soft programming is generally stopped. If a certain number of bits have exceeded ERV1122, and there are still most erased bits that are considered to be too negative, then an erase procedure on the sector which includes the bits may be performed again.
If margin 124 is exceeded by leading edge 120xe2x80x2 of distribution 116xe2x80x2, some least erased bits may exceed read level 126 and, hence be read during a read operation. Since any least erased bit that is read during a read operation will generally cause a failure of a bit during a read operation, an error correction code (ECC) circuit associated with the memory card may correct for the failure. Although the ECC circuit may correct for the least erased bit that exceeds read level 126, the correction of the least erased bit generally takes away from the bandwidth associated with the ECC circuit. For example, in many memory cards, an ECC circuit may be capable of only correcting for four total bits. As such, the correction of the least erased bit that exceeds read level 126 reduces the number of bits read in a read operation which may be corrected to three.
In order to reduce the likelihood that least erased bits exceed read level 126, a second erase verify level (ERV2) may be implemented to enable a least erased bit to be identified before the least erased bit exceeds read level 126. As shown in FIG. 1c, an ERV2140 is typically set such that ERV2140 is within margin 124 such that a new margin 144 may be defined by ERV1122 and ERV2140. That is, ERV2140 may have a higher voltage than ERV1122, and a lower voltage than read level 126. New margin 144 may be selected to meet an erase speed requirement such that if no least erased bits exceed ERV2140, the erase speed associated with the sector is considered to be acceptable. In addition, of no least erased bits exceed ERV2140, then the least erased bits may all still be read as erased bits, and not as read bits.
A certain number of bits may be allowed to exceed ERV1122, and a subset of the bits which exceed ERV1122 may be allowed to exceed ERV2140 before a new erase operation is performed. For example, up to eight total bits may be allowed to exceed ERV1122, with one of the bits also exceeding ERV2140 before a new erase operation is performed. Although a value for ERV2140 may be selected such that the bit that exceeds ERV2140 is not likely to exceed read level 126, the bit that exceeds ERV2140 may in many cases also exceed read level 126.
While soft programming is generally effective in increasing the VT of the most erased bits within a sector, soft programming typically also causes the VT of the least erased bits within the sector to be increased. Shifting or increasing the VT of the least erased bits may reduce the error correction bandwidth of a subsequent read operation, or may require additional erase operations to be performed. Reducing the error correction bandwidth of a subsequent read operation may increase the likelihood of errors occurring during the read operation, while requiring additional erase operations to be performed may be time consuming and, hence, inefficient.
Further, in some cases, soft programming may cause the width of an erase bit threshold voltage distribution, e.g., distribution 116 of FIG. 1a, to be increased. By way of example, when least erased bits shift more than most erased bits, then the width of an erase bit threshold voltage distribution may become wider, thereby affecting the erase speed associated with a sector.
Therefore, what is needed is a method and an apparatus which enables the VT of the most erased bits of a distribution to be increased substantially without causing the VT of the least erased bits of the distribution to be significantly affected. That is, what is desired is a method and an apparatus which enables an erased bit threshold voltage distribution to be substantially tightened.
The present invention relates to a system and a method for tightening an erased bit threshold voltage distribution. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.
In another embodiment, applying the soft program pulse to the over-erased bit to cause the first value to increase includes applying a low voltage to a drain associated with the over-erased bit. In such an embodiment, inhibiting the fast bit may include applying a high voltage to a drain associated with the fast bit wherein the low voltage is approximately zero volts and the high voltage is approximately five volts.
By inhibiting fast or least erased bits during soft programming, the fast bits are effectively not shifted. In other words, inhibiting fast bits essentially prevents soft programming from causing the threshold voltage associated with the fast bits from increasing. As a result, since soft programming enables the threshold voltage associated over-erased or most erased bits to increase in value, an overall erased bit threshold voltage distribution may be tightened.
According to another aspect of the present invention, a memory storage device includes a plurality of memory cells which are each arranged to be associated with an erased bit of a plurality of erased bits. The device also includes means for inhibiting a first erased bit included in the plurality of erased bits which has a first value that is at least approximately equal to a first threshold voltage, as well as means for applying a soft program pulse to the plurality of erased bits. The means for inhibiting the first erased bit substantially prevents the first value from changing and the means for applying the soft program pulse is arranged to substantially cause a second value associated with a second erased bit to change.
According to still another aspect of the present invention, a method for correcting an over-erase condition associated with a non-volatile memory includes providing the non-volatile memory which includes a sector, and performing an erase operation on the sector. The method also includes determining when a first erased bit of a plurality of erased bits associated with the sector is substantially below an over-erased bit threshold. A determination as to whether a second erased bit of the plurality of erased bits associated with the sector is substantially above a first erase verify level is made when it is determined that the first erased bit is substantially below the over-erased bit threshold. The second erased bit is erased when it is determined that the second erased bit is substantially above the first erase verify level, and a first soft program operation is performed on the plurality of erased bits when it is determined that the first erased bit is substantially below the over-erased bit threshold. Performing the first soft program operation on the plurality of erased bits is arranged to cause the first erased bit to shift in a positive direction and to cause the second erased bit to remain substantially unshifted.
In one embodiment, the method also includes determining when the first erased bit is below the over-erased bit threshold after performing the soft program operation, and god performing a second soft program operation on the plurality of erased bits when it is determined that the first erased bit is below the over-erased bit threshold after performing the soft program operation. In another embodiment, the method includes determining when more than an acceptable number of erased bits is substantially above a second erase verify level which is greater than the first erase verify level.